/*
 * Copyright (C) 2019 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2019-01-07 15:09:46
 *
 */


#ifndef ANLG_PHY_G10_H
#define ANLG_PHY_G10_H

#define CTL_BASE_ANLG_PHY_G10 0x403D4000


#define REG_ANLG_PHY_G10_ANALOG_RCO100M_RCO100M_CTRL_0        ( CTL_BASE_ANLG_PHY_G10 + 0x0000 )
#define REG_ANLG_PHY_G10_ANALOG_RCO100M_RTC_CAL_REG_CTRL      ( CTL_BASE_ANLG_PHY_G10 + 0x0004 )
#define REG_ANLG_PHY_G10_ANALOG_RCO100M_REG_SEL_CFG_0         ( CTL_BASE_ANLG_PHY_G10 + 0x0008 )

/* REG_ANLG_PHY_G10_ANALOG_RCO100M_RCO100M_CTRL_0 */

#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC100M_LDO_EN              BIT(22)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC100M_LDO_BYPASS          BIT(21)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC100M_LDO_VOLTAGE_SEL(x)  (((x) & 0x3) << 19)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC100M_LDO_BIAS_SEL(x)     (((x) & 0x3) << 17)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC100M_EN                  BIT(16)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC100M_RC_C(x)             (((x) & 0x7F) << 9)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC100M_RSTB                BIT(8)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC100M_RESERVED(x)         (((x) & 0xFF))

/* REG_ANLG_PHY_G10_ANALOG_RCO100M_RTC_CAL_REG_CTRL */

#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RC100M_CAL_START            BIT(21)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC_CAL_CTL(x)              (((x) & 0x7F) << 14)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC_CAL_SEL                 BIT(13)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RTC_CAL_PRECISION(x)        (((x) & 0xFF) << 5)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RC100M_CAL_DONE             BIT(4)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RCO100M_CAL_SOFT_RST        BIT(3)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RCO100M_2M_CGM_EN           BIT(2)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_26M_2M_CGM_EN               BIT(1)
#define BIT_ANLG_PHY_G10_ANALOG_RCO100M_RCO100M_PHY_SOFT_RST        BIT(0)

/* REG_ANLG_PHY_G10_ANALOG_RCO100M_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_RCO100M_RTC100M_LDO_EN      BIT(4)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_RCO100M_RTC100M_LDO_BYPASS  BIT(3)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_RCO100M_RTC100M_EN          BIT(2)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_RCO100M_RTC100M_RC_C        BIT(1)
#define BIT_ANLG_PHY_G10_DBG_SEL_ANALOG_RCO100M_RTC100M_RSTB        BIT(0)


#endif /* ANLG_PHY_G10_H */


